There is a server which includes a plurality of control circuits (hereinafter also referred to as LSIs (Large Scale Integrated circuits)) and a system control apparatus (hereinafter also referred to as SVP (Service Processor)) that manages and controls the LSIs. In an information processing apparatus such as the server, the SVP and the LSIs are connected by a system control serial bus such as an I2C (Inter-Integrated Circuit) and the SVP manages and controls the LSIs via the system control serial bus.
A multiprocessor system is known in which an SVP and processors are connected by a duplex bus including a simple system bus and a diagnosis bus and a function of a processor in which a failure occurs is backed up by another processor connected to the duplex bus to continue processing.
A method is known in which, in a multi-node information processing apparatus, an initialization command is output from an SVP to a cross bar, and, after the output, the initialization command is output from the cross bar to nodes, whereby the initialization command is output in a tree shape.    Patent Document 1: Japanese Laid-Open Patent Publication No. 6-52130    Patent Document 2: Japanese Laid-Open Patent Publication No. 2007-128285